SH7020 Datasheet, PDF (181/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

CK
RES
A0 to A21
RAS
CAS
RD
RES latch
Tp
timing
Tr
Tc1
Tc2
Manual reset
Row address Colum address FFFF
Figure 8.40 Long - pitch Mode Read (1)
RES latch
timing
CK
Tp
Tr
Tc1
Tc2
RES
A0 to A21
Manual reset
Row address FFFF
RAS
CAS
RD
Figure 8.41 Long - pitch Mode Read (2)
For the signal output shown by solid lines, DRAM data may not be held. Therefore, when DRAM
data must be held after reset, take one of the coutermeasures described as follows.
1. When resetting manually, do this in watchdog timer (WDT) condition.
2. Even if the Low width of RAS becomes as short as 1.5 tcyc as shown above, use with a
frequency that satisfies the DRAM standard (tRAS).
3. Even in case the Low width of RAS has become 1.5 tcyc, proceed by using the external circuit
so that a RAS signal with a Low width of 2.5 tcyc is input in the DRAM (in case the Low
width of RAS is higher than 2.5 tcyc, operate so that the current waveform is input in the
DRAM).
RENESAS 163