SH7020 Datasheet, PDF (130/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

8.2.9 Refresh Time Constant Register (RTCOR)
The refresh time constant register (RTCOR) is a 16-bit read/write register that sets the compare
match cycle used with RTCNT. The values in RTCOR and RTCNT are constantly compared.
When they match, the compare-match flag (CMF) is set in RTCNT and RTCSR is cleared to
H'0000. If the bit RFSHE in RCR is set to 1 when this happens, a CAS before RAS (CBR) refresh
is performed. When the CMIE bit of the RTCSR is also set to 1, a compare match interrupt (CMI)
is generated.
Bits 15–8 are reserved bits and cannot be used to set the cycle. These bits always read as 0.
RTCOR is initialized to H'00FF by a power-on reset, but is not initialized by a manual reset or by
the standby mode.
To prevent RTCOR from being written incorrectly, it must be written by a different method from
most other registers. A word transfer operation is used, H'96 is written in the top byte and the
actual data is written in the lower byte. For details, see section 8.2.11, Note on Register Access.
Bit: 15
14
13
12
11
10
9
8
Bit name: —
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
0
R/W: —
—
—
—
—
—
—
—
Bit: 7
6
5
4
3
2
1
0
Bit name:
Initial value: 1
1
1
1
1
1
1
1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
8.2.10 Parity Control Register (PCR)
The parity control register (PCR) is a 16-bit read/write register that selects the parity polarity and
space to be parity checked. PCR is initialized to H'0000 by a power-on reset, but is not initialized
by a manual reset or by the standby mode.
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