SH7020 Datasheet, PDF (252/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

Bit: 7
6
5
4
3
2
1
0
Bit name: — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0
Initial value:
*
0
0
0
0
0
0
0
R/W: —
Note: Undefined
R/W R/W R/W R/W R/W R/W R/W
• Bit 7 (reserved): Bit 7 is read as undefined. The write value should be 0 or 1.
• Bits 6 and 5 (counter clear 1 and 0 (CCLR1 and CCLR0)): CCLR1 and CCLR0 select the
counter clear source.
Bit 6: Bit 5:
CCLR1 CCLR0 Description
0
0
TCNT is not cleared (initial value)
1
TCNT is cleared by general register A (GRA) compare match or input capture*¹
1
0
TCNT is cleared by general register B (GRB) compare match or input capture*¹
1
Synchronizing clear: TCNT is cleared in synchronization with clear of other
timer counters operating in sync.*²
Notes: 1. When GR is functioning as an output compare register, TCNT is cleared upon a
compare match. When functioning as an input capture register, TCNT is cleared upon
input capture.
2. The timer synchro register (TSNC) set the synchronization.
• Bits 4 and 3 (external clock edge 1/0 (CKEG1 and CKEG0)): CKEG1 and CKEG0 select
external clock input edges. When channel 2 is set for phase counting mode, settings of the
CKEG1 and CKEG0 of the TCR are ignored and the phase counting mode operation takes
priority.
Bit 4:
CKEG
1
0
1
Bit 3:
CKEG
0
0
1
—
Description
Count rising edges (initial value)
Count falling edges
Count both rising and falling edges
• Bits 2–0 (timer prescalar 2–0 (TPS2–TPS0)): TPS2–TPS0 select the counter clock source.
When TPSC2 = 0 and an internal clock source is selected, the timer counts only falling edges.
When TPSC2 = 1 and an external clock is selected, the count edge is as set by CKEG1 and
CKEG0. When the phase counting mode is selected for channel 2 (MDF bit in the timer mode
register is 1), the settings of TPSC2–TPSC0 of TCR2 are ignored and the phase counting
operation takes priority.
236 RENESAS