SH7020 Datasheet, PDF (81/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

IRQOUT
NMI
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
Input
control
UBC
DMAC
ITU
SCI
PRT
WDT
REF
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
Priority
decision
logic
Com-
parator
Interrupt request
SR
I3 I2 I1 I0
CPU
IPR
ICR
IPRA–IPRE
Module bus
Bus
interface
UBC: User break controller
DMAC: Direct memory access controller
ITU: 16-bit integrated-timer pulse unit
SCI: Serial communications interface
PRT: Parity control unit of BSC
INTC
WDT: Watchdog timer
REF: DRAM refresh control unit of BSC
ICR: Interrupt control register
IPRA–IPRE: Interrupt priority registers A–E
SR: Status register
Figure 5.1 Block Diagram of the Interrupt Controller
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