SH7020 Datasheet, PDF (12/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

4.1.1 Exception Processing Types and Priorities .......................................................... 47
4.1.2 Exception Processing Operation .......................................................................... 49
4.1.3 Exception Process Vector Table .......................................................................... 49
4.2 Reset .................................................................................................................................. 51
4.2.1 Reset Types .......................................................................................................... 51
4.2.2 Power-On Reset.................................................................................................... 51
4.2.3 Manual Reset........................................................................................................ 52
4.3 Address Errors ................................................................................................................... 52
4.3.1 Address Error Sources.......................................................................................... 52
4.3.2 Address Error Exception Processing.................................................................... 53
4.4 Interrupts............................................................................................................................ 54
4.4.1 Interrupt Sources .................................................................................................. 54
4.4.2 Interrupt Priority Rankings................................................................................... 54
4.4.3 Interrupt Exception Processing ............................................................................ 55
4.5 Instruction Exceptions ....................................................................................................... 55
4.5.1 Types of Instruction Exceptions........................................................................... 55
4.5.2 Trap Instruction .................................................................................................... 55
4.5.3 Illegal Slot Instruction .......................................................................................... 56
4.5.4 General Illegal Instructions .................................................................................. 56
4.6 Cases in Which Exceptions Are Not Accepted ................................................................. 57
4.6.1 Immediately after Delayed Branch Instructions................................................... 57
4.6.2 Immediately after Interrupt-Disabling Instructions.............................................. 57
4.7 Stack Status after Exception Processing............................................................................ 58
4.8 Notes.................................................................................................................................. 59
4.8.1 Value of the Stack Pointer (SP)............................................................................ 59
4.8.2 Value of the Vector Base Register (VBR) ........................................................... 59
4.8.3 Address Errors that Are Caused by Stacking During Address Error
Exception Processing............................................................................................ 59
Section 5 Interrupt Controller (INTC) .......................................................................... 61
5.1 Overview............................................................................................................................ 61
5.1.1 Features ................................................................................................................ 61
5.1.2 Block Diagram...................................................................................................... 61
5.1.3 Pin Configuration ................................................................................................. 63
5.1.4 Registers ............................................................................................................... 63
5.2 Interrupt Sources................................................................................................................ 63
5.2.1 NMI Interrupts...................................................................................................... 64
5.2.2 User Break Interrupt ............................................................................................. 64
5.2.3 IRQ Interrupts ...................................................................................................... 64
5.2.4 On-Chip Interrupts................................................................................................ 64
5.2.5 Interrupt Exception Vectors and Priority Rankings ............................................. 65
5.3 Register Descriptions......................................................................................................... 68
5.3.1 Interrupt Priority Registers A–E (IPRA–IPRE) ................................................... 68