SH7020 Datasheet, PDF (17/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

11.2.2 Port B Data Register (PBDR)............................................................................... 307
11.2.3 Next Data Register A (NDRA) ............................................................................ 308
11.2.4 Next Data Register B (NDRB) ............................................................................. 310
11.2.5 Next Data Enable Register A (NDERA).............................................................. 311
11.2.6 Next Data Enable Register B (NDERB) .............................................................. 312
11.2.7 TPC Output Control Register (TPCR) ................................................................. 313
11.2.8 TPC Output Mode Register (TPMR) ................................................................... 314
11.3 Operation ........................................................................................................................... 316
11.3.1 Overview .............................................................................................................. 316
11.3.2 Output Timing ...................................................................................................... 317
11.3.3 Examples of Use of Ordinary TPC Output .......................................................... 317
11.3.4 TPC Output Non-Overlap Operation.................................................................... 320
11.3.5 TPC Output by Input Capture .............................................................................. 324
11.4 Usage Notes ....................................................................................................................... 325
11.4.1 Non-Overlap Operation........................................................................................ 325
Section 12 Watchdog Timer (WDT) ............................................................................ 327
12.1 Overview............................................................................................................................ 327
12.1.1 Features ................................................................................................................ 327
12.1.2 Block Diagram...................................................................................................... 328
12.1.3 Pin Configuration ................................................................................................. 328
12.1.4 Register Configuration ......................................................................................... 329
12.2 Register Descriptions......................................................................................................... 329
12.2.1 Timer Counter (TCNT) ........................................................................................ 329
12.2.2 Timer Control/Status Register (TCSR) ................................................................ 330
12.2.3 Reset Control/Status Register (RSTCSR) ............................................................ 331
12.2.4 Register Access .................................................................................................... 333
12.3 Operation ........................................................................................................................... 334
12.3.1 Operation in the Watchdog Timer Mode.............................................................. 334
12.3.2 Operation in the Interval Timer Mode.................................................................. 336
12.3.3 Operation in the Standby Mode............................................................................ 336
12.3.4 Timing of Setting the Overflow Flag (OVF)........................................................ 337
12.3.5 Timing of Setting the Watchdog Timer Overflow Flag (WOVF)........................ 337
12.4 Usage Notes ....................................................................................................................... 338
12.4.1 TCNT Write and Count Up Contention ............................................................... 338
12.4.2 Changing CKS2-CKS0 Bit Values ...................................................................... 338
12.4.3 Changing Watchdog Timer/Interval Timer Modes .............................................. 338
12.4.4 System Reset With WDTOVF ............................................................................. 339
12.4.5 Internal Reset With the Watchdog Timer ............................................................ 339
Section 13 Serial Communication Interface (SCI) .................................................. 341
13.1 Overview............................................................................................................................ 341
13.1.1 Features ................................................................................................................ 341