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SH7020 Datasheet, PDF (233/509 Pages) Renesas Technology Corp – SuperH™ RISC engine | |||
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Block Diagram of Channels 0 and 1: ITU channels 0 and 1 have the same function. Figure 10.2
is a block diagram of channels 0 and 1.
TCLKAâ
TCLKD
Ï, Ï/2,
Ï/4, Ï/8
Clock selection
Comparator
Control logic
TIOCAn
TIOCBn
IMIAn
IMIBn
OVIn
Module data bus
TCNTn: Timer counter n (16 bits)
GRAn, GRBn: General registers An, Bn (input capture/output compare dual use) (16 bits à 2)
TCRn: Timer control register n (8 bits)
TIORn: Timer I/O control register n (8 bits)
TIERn: Timer interrupt enable register n (8 bits)
TSRn: Timer status register n (8 bits) (n = 0 or 1)
Figure 10.2 Channels 0 and 1 Block Diagram (One Channel Shown)
RENESAS 217
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