SH7020 Datasheet, PDF (213/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

DREQ
Bus right returned to CPU
Bus cycle
CPU
CPU CPU DMAC DMAC CPU DMAC DMAC CPU
Read Write
Read Write
Figure 9.10 Transfer Example in the Cycle-Steal Mode (Dual address mode, DREQ level
detection)
• Burst Mode
Once the bus right is obtained, the transfer is performed continuously until the transfer end
condition is satisfied. In the external request mode with low level detection of the DREQ pin,
however, when the DREQ pin is driven high, the bus passes to the other bus master after the
bus cycle of the DMAC that currently has an acknowledged request ends, even if the transfer
end conditions have not been satisfied.
The burst mode cannot be used when the serial communications interface (SCI) is the transfer
request source. Figure 9.11 shows an example of DMA transfer timing in the burst mode. The
transfer conditions shown in the figure are:
 Single address mode
 DREQ level detection
DREQ
Bus cycle _{CPU CPU CPU DMAC DMAC DMAC DMAC DMAC DMAC CPU}
Figure 9.11 Transfer Example in the Burst Mode (Single address mode, DREQ level
detection)
Relationship between Request Modes and Bus Modes by DMA Transfer Category: Table 9.6
shows the relationship between request modes and bus modes by DMA transfer category.
196 RENESAS