SH7020 Datasheet, PDF (274/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

10.4.4 PWM Mode
The PWM mode is controlled using both the GRA and GRB in pairs. The PWM waveform is
output from the TIOCA output pin. The PWM waveform’s 1 output timing is set in GRA and the 0
output timing is set in GRB. A PWM waveform with duty cycle between 0% and 100% can be
output from the TIOCA pin by having either compare match GRA or GRB be the counter clear
source for the timer counter. All five channels can be set to PWM mode.
Table 10.11 lists the combinations of PWM output pins and registers. Note that when the GRA
and GRB are set to the same value, the output will not change even if a compare match occurs.
Table 10.11 Combinations of PWM Output Pins and Registers
Channel
0
1
2
3
4
Output Pin
TIOCA0
TIOCA1
TIOCA2
TIOCA3
TIOCA4
1 Output
GRA0
GRA1
GRA2
GRA3
GRA4
0 Output
GRB0
GRB1
GRB2
GRB3
GRB4
Procedure for Selecting the PWM Mode (figure 10.28):
1. Set bits TPSC2–TPSC0 in the TCR to select the counter clock source. If an external clock
source is selected, set bits CKEG1 and CKEG0 in the TCR to select the desired edges of the
external clock signal.
2. Set CCLR1 and CCLR0 in the TCR to select the counter clear source.
3. Set the time at which the PWM waveform should go to 1 in the GRA.
4. Set the time at which the PWM waveform should go to 0 in the GRB.
5. Set the PWM bit in TMDR to select the PWM mode. When the PWM mode is selected,
regardless of the contents of TIOR, the GRA and GRB become output compare registers
specifying the times at which the PWM waveform goes high and low. TIOCA automatically
becomes a PWM output pin. TIOCB becomes whatever is set in the TIOR's IOB1 and IOB0
bits.
6. Set the STR bit in the TSTR to let the TCNT start counting.
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