SH7020 Datasheet, PDF (59/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

Table 2.17 System Control Instructions (cont)
Instruction
Instruction Code Operation
Execution T bit
Cycles
STS.L MACH,@–Rn 0100nnnn00000010 Rn–4 → Rn, MACH → (Rn) 1
—
STS.L MACL,@–Rn 0100nnnn00010010 Rn–4 → Rn, MACL → (Rn) 1
—
STS.L PR,@–Rn 0100nnnn00100010 Rn–4 → Rn, PR → (Rn)
1
—
TRAPA #imm
11000011iiiiiiii PC/SR → stack area,
8
—
(imm×4+VBR) → PC
Note:
Instruction execution cycles: The execution cycles shown in the table are minimums. The
actual number of cycles may be increased:
1. When contention occurs between instruction fetches and data access, or
2. When the destination register of the load instruction (memory → register) and the
register used by the next instruction are the same.
38 RENESAS