SH7020 Datasheet, PDF (25/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

Table 1.1 Features of the SH7032 and SH7034 Microcomputers (cont)
Feature
Description
Direct memory access
controller (DMAC)
(4 channels)
Permits DMA transfer between the following modules:
• External memory
• External I/O
• On-chip memory
• Peripheral on-chip modules (except DMAC)
DMA transfer can be requested from external pins, on-chip SCI, on-
chip timers, and on-chip A/D converter
Cycle-steal mode or burst mode
Channel priority level is selectable
Channels 0 and 1: dual or single address transfer mode is
selectable; external request sources are supported; Channels 2 and
3: dual address transfer mode, internal request sources only
16-bit integrated-timer
pulse unit (ITU)
Ten types of waveforms can be output
Input pulse width and cycle can be measured
PWM mode: pulse output with 0–100% duty cycle (maximum
resolution: 50 ns)
Complementary PWM mode: can output a maximum of three pairs
of non-overlapping PWM waveforms
Phase counting mode: can count up or down according to the phase
of an external two-phase clock
Timing pattern controller
(TPC)
Maximum 16-bit output (4 bits × 4 channels) can be output
Non-overlap intervals can be established between pairs of
waveforms
Timing-source timer is selectable
Watchdog timer (WDT)
(1 channel)
Can be used as watchdog timer or interval timer
Timer overflow can generate an internal reset, external signal, or
interrupt
Power-on reset or manual reset can be selected as the internal reset
Serial communication
Asynchronous or clocked synchronous mode is selectable
interface (SCI) (2 channels) _{Can transmit and receive simultaneously (full duplex)}
On-chip baud rate generator in each channel
Multiprocessor communication function
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