SH7020 Datasheet, PDF (433/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

SH7020
Internal data bus (32 bits)
H'0000000
H'0000004
H'0000001
H'0000005
H'0000002
H'0000006
H'0000003
H'0000007
H'0003FFC
SH7021
On-chip ROM
H'0003FFD
H'0003FFE
Internal data bus (32 bits)
H'0003FFF
H'0000000
H'0000004
H'0000001
H'0000005
H'0000002
H'0000006
H'0000003
H'0000007
On-chip ROM
H'0007FFC
H'0007FFD
H'0007FFE
H'0007FFF
Note: The addresses shown in the figure are the first shadow addresses in the on-chip ROM
space.
Figure 16.1 Block Diagram of ROM
The operating mode determines whether the on-chip ROM is valid or not. The operating mode is
selected using mode-setting pins MD0-MD2 as shown in table17.1. If you are using the on-chip
ROM, select mode 2; if you are not, select mode 0 or 1. The on-chip ROM is allocated to address
H'0000000–H'0003FFF (SH7020), H'0000000–H'0007FFF (SH7021) of memory area 0. Memory
area 0 (H'0000000-H'0FFFFFF and H'8000000–H'8FFFFFF) is divided into 16-kbyte (SH7020) or
32-kbyte (SH7021) shadows. No matter which shadow is accessed, the on-chip ROM is accessed.
See section 8, Bus State Controller, for more information on shadows.
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