SH7020 Datasheet, PDF (217/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

CK
DREQ
Bus cycle
CPU CPU CPU DMAC CPU CPU CPU CPU
DACK
Figure 9.15 DREQ Sampling Timing in Cycle Steal Mode (Output with DREQ level
detection and DACK active low) (Single address mode, bus cycle = 2 states)
CK
DREQ
Bus cycle
CPU CPU CPU DMAC (R) DMAC (W) CPU CPU CPU
DACK
DMAC (R): DMAC read cycle
DMAC (W): DMAC write cycle
Note: Illustrates the case when DACK is output during the DMAC write cycle.
Figure 9.16 DREQ Sampling Timing in Cycle Steal Mode (Output with DREQ level
detection and DACK active low) (Dual address mode, bus cycle = 2 states)
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