SH7020 Datasheet, PDF (135/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

As figure 8.4 shows, specific spaces such as DRAM space and address/data multiplexed I/O space
are allocated to the 8 areas. Each of the spaces is equipped with the necessary interfaces. The
control signals needed by DRAM and peripheral LSIs will be output by the chip to devices
connected to an area allocated to the appropriate type of space.
8.3.2 Bus Width
The primary bus width selection on for this chip is made by switching between 8-bit and 16 bit
using the A27 bit. When A27 is 0, the bus width is 8 bits and data is input/output through the
AD7–AD0 pins; when A27 is 1, the size is 16 bits and data is input/output through the AD15–
AD0 pins for word accesses. For byte access, the top byte is input/output through AD15–AD8 and
the lower byte through AD7–AD0. When the bus width is 8 bits or byte access is being performed
with a 16-bit bus width, the status of the eight AD pins that are not inputting/outputting data is as
shown in appendix B, Pin States.
Bus widths are also determined by conditions other than the A27 bit for specific areas:
• Area 0 is an 8-bit external memory space when the MD2–MD0 pins are 000, a 16-bit external
memory space when the same bits are 001, and a 32-bit on-chip ROM space when they are
010.
• Area 5 is an 8-bit on-chip peripheral module space when the A27 bit and A8 bit are both 0 and
a 16-bit on-chip peripheral module space when the A27 bit is 0 and the A8 bit is 1. When the
A27 bit is 1, it is a 16-bit external memory space.
• Area 6 is an 8-bit bus width when the A27 bit and A14 bit are both 0 and a 16-bit bus width
when the A27 bit is 0 and the A14 bit is 1. When the A27 bit is 1, it is a 16-bit space.
• Area 7 is a 32-bit on-chip RAM space when the A27 bit is 1 and an 8-bit external memory
space when the A27 bit is 0.
Word (16-bit) data accessed from 8-bit bus areas and longword (32-bit) data accessed from 16-bit
bus areas require two consecutive accesses. Longword (32-bit) data accessed from 8-bit bus areas
requires four consecutive accesses.
8.3.3 Chip Select Signals (CS0–CS7)
When the A26–A24 bits of the address are decoded, they become chip select signals (CS0–CS7)
for areas 0–7. When an area is accessed, the corresponding chip select pins are driven low. Table
8.7 shows the relationship between the A26–A24 bits and the chip select signals.
RENESAS 117