SH7020 Datasheet, PDF (490/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

T_p
T_r
T_c
CK
t_AD
t_AD
A21–A0
Row
Column
RAS
CAS
t_RASD1
t_RAH
t_RASD2
t_RDD
t_DS
t_ASC
t_CASD1
t_RSD
RD(Read)
WRH, WRL,
(Read)
DACK0
DACK1
(Read)
AD15–AD0
DPH, DPL
(Read)
t_WCH
t_DACD1 t_DACD2
t_ACC1*^{2 tCAC1*1}
t_RAC1*³
t_RDS
t_RDH*⁴
RD(Write)
WRH, WRL,
(Write)
AD15–AD0
(Write)
t_WSD3
t_WCS
t_WDD2
t_WSD4
t_WDH
DPH, DPL
(Write)
t_WPDD2
t_WPDH
DACK0
DACK1
(Write)
t_DACD4 t_DACD5
Notes: 1.
2.
3.
4.
For t_CAC1, use t_cyc × 0.65 – 35 (for 35% duty) or t_cyc × 0.5 – 35 (for 50% duty)
instead of t_cyc – t_AD – t_ASC – t_RDS.
For t_ACC1, use t_cyc – 44 instead of t_cyc – t_AD – t_RDS.
For t_RAC1, use t_cyc × 1.5 – 35 instead of t_cyc × 1.5 – t_RASD1 – t_RDS.
t_RDH is measured from A21–A0, RAS, or CAS, whichever is negated first.
Figure 19.24 DRAM Bus Cycle (Short Pitch, Normal Mode)
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