SH7020 Datasheet, PDF (32/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

Table 1.3 Pin Functions (cont)
Type
Symbol Pin No. I/O Name and Function
Bus
RAS
52
control
O Row address strobe: DRAM row-address strobe-timing
signal.
(cont)
CASH
47
O Column address strobe high: DRAM column-address
strobe-timing signal outputs low level to access the
upper eight data bits.
CASL
49
O Column address strobe low: DRAM column-address
strobe-timing signal outputs low level to access the
lower eight data bits.
RD
57
O Read: Indicates reading of data from an external device.
WRH
56
O Upper write: Indicates write access to the upper eight
bits of an external device.
WRL
55
O Lower write: Indicates write access to the lower eight
bits of an external device.
CS0–CS7 46–49, O Chip select 0–7: Chip select signals for accessing
51–54
external memory and devices.
AH
61
O Address hold: Address hold timing signal for a device
using a multiplexed address/data bus.
HBS, LBS 20, 56 O Upper/lower byte strobe: Upper and lower byte strobe
signals. (Also used as WRH and A0.)
WR
55
O Write: Brought low during write access. (Also used as
WRL.)
DMAC
DREQ0, 66, 68 I
DREQ1
DMA transfer request (channels 0 and 1): Input pins for
external DMA transfer requests.
DACK0, 65, 67 O DMA transfer acknowledge (channels 0 and 1):
DACK1
Indicates that DMA transfer is acknowledged.
16-bit
integrated-
timer pulse
unit (ITU)
TIOCA0,
TIOCB0
TIOCA1,
TIOCB1
51, 53
62, 64
I/O ITU input capture/output compare (channel 0): Input
capture or output compare pins.
I/O ITU input capture/output compare (channel 1): Input
capture or output compare pins.
TIOCA2, 83, 84
TIOCB2
I/O ITU input capture/output compare (channel 2): Input
capture or output compare pins.
TIOCA3, 85, 86
TIOCB3
I/O ITU input capture/output compare (channel 3): Input
capture or output compare pins.
TIOCA4, 87, 89
TIOCB4
I/O ITU input capture/output compare (channel 4): Input
capture or output compare pins.
RENESAS 11