SH7020 Datasheet, PDF (318/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

Table 10.22 ITU Operating Modes (Channel 4) (cont)
Counter Clear Function
Register Setting
TSNC
TMDR
TFCR
TOCR
TIOR4
TCR4
Reset
Output
Operating
Comp Sync Buf- Level
Mode Sync MDF FDIR PWM PWM PWM fer Select IOA
Clear Clock
IOB Select Select
Synch- SYNC4 — — √
CMD1 √*³ √
—
√
√
CCLR1 √
ronized = 1
= 1,
=1
clear
CMD1
CCLR0
=0
=1
inhibit
ed
Comple- √*² — — —
CMD1 CMD1 √
√
—
—
CCLR1 √*⁴
mentary
=1 =1
=0
PWM
CMD0 CMD0
CCLR0
=0 =0
=0
Reset √
— — — CMD1 CMD1 √ √
—
—
√*⁵ √*⁵
synchron-
=1 =1
ized PWM
CMD0 CMD0
=1 =1
Buffer √
(BRA)
——√
√ √ BFA4 — √
= 1,
others
free
√
√
√
Buffer √
(BRB)
——√
√ √ BFB4 — √
= 1,
others
free
√
√
√
√: Settable, —: Setting does not affect current mode
Notes: 1. In PWM mode, the input capture function cannot be used. When compare match A and
compare match B occur simultaneously, the compare match signal is inhibited.
2. When set for complementary PWM mode, do not simultaneously set channel 3 and
channel 4 to function synchronously.
3. Counter clearing works with the reset-synchronized PWM mode, but TCNT4 runs
independently. The output waveform is not affected.
4. Clock selection when the complementary PWM mode is set should be the same for
channels 3 and 4.
5. In the reset-synchronized PWM mode, TCNT4 runs independently. The output
waveform is not affected.
302 RENESAS