SH7020 Datasheet, PDF (358/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

13.1.3 Input/Output Pins
Table 13.1 summarizes the SCI pins by channel.
Table 13.1 SCI Pins
Channel
0
1
Pin Name
Serial clock pin
Receive data pin
Transmit data pin
Serial clock pin
Receive data pin
Transmit data pin
Abbreviation
SCK0
RxD0
TxD0
SCK1
RxD1
TxD1
Input/Output
Input/output
Input
Output
Input/output
Input
Output
Function
SCI0 clock input/output
SCI0 receive data input
SCI0 transmit data output
SCI1 clock input/output
SCI1 receive data input
SCI1 transmit data output
13.1.4 Register Configuration
Table 13.2 summarizes the SCI internal registers. These registers select the communication mode
(asynchronous or clocked synchronous), specify the data format and bit rate, and control the
transmitter and receiver sections.
Table 13.2 Registers
Channel Address*¹ Name
Abbreviation R/W
Initial Access
Value size
0
H'05FFFEC0 Serial mode register SMR0
R/W H'00 8, 16
H'05FFFEC1 Bit rate register
BRR0
R/W H'FF 8, 16
H'05FFFEC2 Serial control register SCR0
R/W H'00 8, 16
H'05FFFEC3 Transmit data register TDR0
R/W H'FF 8, 16
H'05FFFEC4 Serial status register SSR0
R/(W)*² H'84 8, 16
H'05FFFEC5 Receive data register RDR0
R
H'00 8, 16
1
H'05FFFEC8 Serial mode register SMR1
R/W H'00 8, 16
H'05FFFEC9 Bit rate register
BRR1
R/W H'FF 8, 16
H'05FFFECA Serial control register SCR1
R/W H'00 8, 16
H'05FFFECB Transmit data register TDR1
R/W H'FF 8, 16
H'05FFFECC Serial status register SSR1
R/(W)*² H'84 8, 16
H'05FFFECD Receive data register RDR1
R
H'00 8, 16
Notes: 1. Only the values of bits A27–A24 and A8-A0 are valid; bits A23–A9 are ignored. For
details on the register addresses, see section 8.3.5, Description of Areas.
2. Write 0 to clear flags.
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