SH7020 Datasheet, PDF (444/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

Section 18 Power-Down States
18.1 Overview
In the power-down mode, all CPU functions are halted. This lowers power consumption
dramatically.
18.1.1 Power-Down Modes
The SH microprocessor has two power-down modes.
1. Sleep mode
2. Standby mode
The sleep mode and standby mode are entered from the program execution state according to the
transition conditions given in table 18.1. Table 18.1 also describes procedures for canceling each
mode and the states of the CPU and peripheral functions.
Table 18.1 Power-Down States
State
Entering
Peripheral CPU
I/O
Mode Procedure Clock CPU Functions Registers RAM Ports
Canceling
Procedure
Sleep
mode
Execute Run
SLEEP
instruction
with SBY
bit set to 0
in SBYCR
Halt Run
Held
Held Held
• Interrupt
• DMA
address
error
• Power-on
reset
• Manual
reset
Standb Execute Halt
y mode SLEEP
instruction
with SBY
bit set to 1
in SBYCR
Halt Halt*¹
Held
Held
Held or
high-Z*²
• NMI
• Power-on
reset
• Manual
reset
SBYCR: Standby control register
SBY: Standby bit
Notes: 1. Some of the registers of the on-chip peripheral modules are not initialized in the
standby mode. For details, see table 18.3, Status of Registers in the Standby Mode in
section 18.4.1, Transition to the Standby Mode, or the descriptions of registers given
where the on-chip peripheral modules are covered.
2. The status of I/O ports in the standby mode are set by the port high-impedance bit (HIZ)
of the SBYCR. See section 18.2, Standby Control Register (SBYCR) for details. The
status of pins other than the I/O ports are described in appendix B, Pin States.
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