SH7020 Datasheet, PDF (210/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

The DACK output when a transfer occurs from an external device with DACK to a memory-
mapped external device is the write waveform. The DACK output when a transfer occurs from
a memory-mapped external device to an external device with DACK is the read waveform.
The setting of the acknowledge mode (AM) bits in the channel control registers (CHCR0,
CHCR1) have no effect.
CK
A21–A0
CSn
D15–D0
DACK
WRH
WRL
Address output to external memory space
Data that is output from the external
device with DACK
DACK signal to external devices with
DACK (active low)
WR signal to external memory space
(a) External device with DACK to external memory space
CK
A21–A0
CSn
D15–D0
RD
DACK
Address output to external memory space
Data that is output from external memory space
RD signal to external memory space
DACK signal to external device with DACK
(active low)
(b) External memory space to external device with DACK
Figure 9.7 Example of DMA Transfer Timing in the Single Address Mode
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