SH7020 Datasheet, PDF (467/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

Table 19.6 Bus Timing (1) (cont)
Conditions: V_CC = 5.0 V ±10%, V_SS = 0 V, φ = 20 MHz, Ta = –20 to +75°C*
*: Normal products. Ta = –40 to +85°C for wide-temperature range products.
Item
Symbol Min Max
Unit Figures
AH delay time 1
AH delay time 2
Multiplexed address delay
time
t_AHD1
t_AHD2
t_MAD
— 20
— 20
— 30
ns 19.19
ns
ns
Multiplexed address hold time t_MAH
0—
DACK0, DACK1 delay time 1 t_DACD1 — 23
ns
ns 19.8, 19.9, 19.11–
19.14, 19.19, 19.20
DACK0, DACK1 delay time 2 t_DACD2 — 23
DACK0, DACK1 delay time 3 t_DACD3 — 20
ns
ns 19.9, 19.13, 19.14,
19.19
DACK0, DACK1 delay time 4 t_DACD4 — 20
ns 19.11, 19.12
DACK0, DACK1 delay time 5 t_DACD5 — 20
ns
Read delay time 35% duty^*2 t_RDD
50% duty
— t_cyc × 0.35 + 12 ns 19.8, 19.9, 19.11-
—
t_cyc × 0.5 + 15
ns
19.15, 19.19, 19.24-
19.28
Data setup time for CAS
CAS setup time for RAS
Row address hold time
Write command hold time
Write command 35% duty^*2
setup time
50% duty
t_DS
t_CSR
t_RAH
t_WCH
t_WCS
0^*5 —
10 —
10 —
15 —
0—
0—
ns 19.11, 19.13
ns 19.16, 19.17, 19.18
ns 19.11, 19.13
ns
ns 19.11
ns
Access time from CAS
precharge^*6
t_ACP
t_cyc —
− 20
ns 19.12
Notes: 1. HBS and LBS signals are 25 ns.
2. When frequency is 10 MHz or more.
3. n is the number of wait cycles.
4. Access time from addresses A0 to A21 is tcyc-25.
5. –5 ns for parity output of DRAM long-pitch access.
6. It is not necessary to meet the t_RDS specification as long as the access time
specification is met.
RENESAS 457