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SH7020 Datasheet, PDF (477/509 Pages) Renesas Technology Corp – SuperH™ RISC engine
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CK
A21–A0
RAS
CAS
RD(Read)
WRH, WRL,
(Read)
AD15–AD0
DPH, DPL
(Read)
DACK0
DACK1
(Read)
RD(Write)
WRH, WRL,
(Write)
AD15–AD0
(Write)
DPH, DPL
(Write)
DACK0
DACK1
(Write)
Tp
Tr
Tc1
Tc2
tAD
tAD
tRASD1
Row
tRAH
tRDD
Column
tDS
tCASD2
tRASD2
tCASD3
tRSD
tRAC2*3 tACC2*2
tWCH
tCAC2*1
tRDS
tRDH*4
tDACD1
tDACD2
tWSD1
tWSD2
tWDD1
tWDH
tWPDD1
tWPDH
tDACD3
tDACD3
Notes: 1.
2.
3.
4.
For tCAC2, use tcyc × (n + 1) – 25 instead of tcyc × (n + 1) – tCASD2 – tRDS.
For tACC2, use tcyc × (n + 2) – 30 instead of tcyc × (n + 2) – tAD – tRDS.
For tRAC2, use tcyc × (n + 2.5) – 20 instead of tcyc × (n + 2.5) – tRASD1 – tRDS.
tRDH is measured from A21–A0, CAS, or RAS, whichever is negated first.
Figure 19.13 DRAM Bus Cycle: (Long Pitch, Normal Mode)
RENESAS 467
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