SH7020 Datasheet, PDF (110/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

No crossing
signal lines
C_L1
XTAL
C_L2
EXTAL
Figure 7.6 Precaution on Oscillator Circuit Board Design
Duty cycle correction circuit: Duty cycle corrections are conducted for an input clock over 5
MHz. Duty cycles may not be corrected if under 5 MHz, but AC characteristics for the high-level
pulse width (t_CH) and low-level pulse width (t_CL) of the clock are satisfied, and the LSI will
operate normally. Figure 7.7 shows the standard characteristics of a duty cycle correction.
This duty cycle correction circuit is not for correcting the input clock's transient fluctuations and
jutters.
Input duty
70
70
60
60
50
50
40
40
30
30
1
2
5
10
20
(MHz)
Input frequency
Figure 7.7 Duty Cycle Correction Circuit Standard Characteristics
92 RENESAS