SH7020 Datasheet, PDF (335/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

Five-Phase Pulse Output (figure 11.5):
1. Set the GRA of the ITU that serves as output trigger as the output compare register. Set the
cycle time in the GRA of the ITU and select to clear the counter upon compare match A. Set
the IMIEA bit of TIER to 1 to enable the compare match A interrupt.
2. Write H'FFC0 in the PBCR1, write H'F8 in the NDERB, and set G3CMS0, G3CMS1,
G2CMS1 and G2CMS0 in the TPCR to set the ITU compare match selected in step 1 as the
output trigger. Write output data H'80 in the NDRB.
3. When the selected ITU channel starts operating and a compare-match occurs, the values in the
NDRB are transferred to the PBDR and output. The compare-match/input capture A (IMIA)
interrupt service routine writes the next output data (H'C0) in the NDRB.
4. Five-phase pulse output can be obtained by writing H'40, H'60, H'20, H'30, H'10, H'18, H'08,
H'88… at successive compare-match interrupts. If the DMA controller is set for activation by
compare-match, pulse output can be obtained without loading the CPU.
TCNT
value TCNT
GRA
Compare matches
H'0000
NDRB 80 C0 40 60 20 30 10 18 08 88 80 C0
Time
PBDR
8000 C000 4000 6000 2000 3000 1000 1800 0800 8800 8000 C000
TP15
TP14
TP13
TP12
TP11
Figure 11.5 TPC Output Example (5-Phase Pulse Output)
RENESAS 319