SH7020 Datasheet, PDF (117/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

Bit:
Bit name:
Initial value:
R/W:
15
RW7
1
R/W
14
RW6
1
R/W
13
RW5
1
R/W
12
RW4
1
R/W
11
RW3
1
R/W
10
RW2
1
R/W
9
RW1
1
R/W
8
RW0
1
R/W
Bit: 7
6
5
4
3
2
1
0
Bit name: —
—
—
—
—
—
WW1
—
Initial value: 1
1
1
1
1
1
1
1
R/W: —
—
—
—
—
—
R/W
—
• Bits 15–8 (wait state control during read (RW7–RW0)): RW7–RW0 determine the number of
states in read cycles for each area and whether or not to sample the signal input from the
WAIT pin. Bits RW7–RW0 correspond to areas 7–0, respectively. If a bit is cleared to 0, the
WAIT signal is not sampled during the read cycle for the corresponding area. If it is set to 1,
sampling takes place.
For the external memory spaces of areas 1, 3–5, and 7, read cycles are completed in one state
when the corresponding bits are cleared to 0. When they are set to 1, the number of wait states
is 2 plus the WAIT signal value. For the external memory space of areas 0, 2, and 6, read
cycles are completed in one state plus the number of long wait states (set in wait state
controller 3 (WCR3)) when the corresponding bits are cleared to 0. When they are set to 1, the
number of wait states is 1 plus the long wait state; when the WAIT signal is at low level as
well, a wait state is inserted.
The DRAM space (area 1) finishes the column address output cycle in one state (short pitch)
when the RW1 bit is 0, and in 2 states plus the WAIT signal value (long pitch) when RW1 is 1.
When RW1 is set to 1, the number of wait states selected in wait state insertion bits 1 and 0
(RLW0 and RLW1) for CAS-before-RAS (CBR) refresh of the refresh control register (RCR)
are inserted during the CBR refresh cycle, regardless of the status of the WAIT signal.
The read cycle of the address/data multiplexed I/O space (area 6) is 4 states plus the wait states
from the WAIT signal, regardless of the setting of the RW6 bit. The read cycle of the on-chip
peripheral module space (area 5) finishes in 3 states, regardless of the setting of the RW5 bit,
and the WAIT signal is not sampled. The read cycles of on-chip ROM (area 0) and on-chip
RAM (area 7) finish in 1 state, regardless of the settings of bits RW0 and RW7. The WAIT
signal is not sampled for either.
Table 8.3 summarizes read cycle state information.
RENESAS 99