SH7020 Datasheet, PDF (46/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

Table 2.8 Addressing Modes and Effective Addresses (cont)
Addressing Mnemonic
Mode
Expression Effective Addresses Calculation
Immediate #imm:8
addressing
The 8-bit immediate data (imm) for the TST, AND,
OR, and XOR instructions are zero-extended.
#imm:8
The 8-bit immediate data (imm) for the MOV, ADD,
and CMP/EQ instructions are sign-extended.
#imm:8
Immediate data (imm) for the TRAPA instruction is
zero-extended and is quadrupled.
Equation
—
—
—
2.3.3 Instruction Formats
The instruction format refers to the source operand and the destination operand. The meaning of
the operand depends on the instruction code. Symbols are as follows.
xxxx Instruction code
mmmm Source register
nnnn Destination register
iiii
Immediate data
dddd Displacement
Table 2.9 Instruction Formats
Instruction Formats
0 format
15
xxxx xxxx xxxx
0
xxxx
Source
Operand
—
n format
—
Destination
Operand
—
Instruction
Example
NOP
nnnn: Direct
register
MOVT Rn
15
xxxx nnnn
0
xxxx xxxx
Control register
or system
register
Control register
or system
register
nnnn: Direct
register
STS MACH,Rn
nnnn: Indirect pre- STC.L SR,@-Rn
decrement register
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