SH7020 Datasheet, PDF (157/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

T_p1
T_p2
T_r
CK
T_c1
T_c2
A21–A0
Row address
Column address
RAS
CAS
Figure 8.19 Precharge Timing (Long Pitch)
Control of Insertion of Wait States Using the WAIT Pin Input Signal: The number of wait
states inserted into the DRAM access cycle can be controlled by setting WCR1 and WCR2. When
the corresponding bits in WCR1 and WCR2 are cleared to 0, the column address output cycle ends
in 1 state and no wait states are inserted. When the bit is 1, the WAIT pin input signal is sampled
on the rise of the system clock (CK) directly preceding the second state of the column address
output cycle and the wait state is inserted as long as the level is low. When a high level is detected,
it shifts to the second state. Figure 8.20 shows the wait state timing in a long pitch bus cycle.
T_p
CK
T_r
T_c1 T_cw (wait state)
T_c2
A21–A0
Row address
Column address
RAS
CAS
WAIT
Figure 8.20 Wait State Timing during DRAM Access (Long Pitch)
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