SH7020 Datasheet, PDF (448/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

Table 18.3 Register States in the Standby Mode
Module
Interrupt controller (INTC)
User break controller (UBC)
Bus state controller (BSC)
Pin function controller (PFC)
I/O ports
Direct memory access controller
(DMAC)
Watchdog timer (WDT)
16-bit integrated timer pulse unit
(ITU)
Programmable timing pattern
controller (TPC)
Serial communications interface
(SCI)
Power-down state register
Register Initialized
—
—
—
—
—
All registers
Registers That Hold Data
All registers
All registers
All registers
All registers
All registers
—
• Bits 7–5 (OVF, WT/IT, TME)
of the timer control status
register (TCSR)
• Reset control/status register
(RSTCSR)
All registers
• Bits 2–0 (CKS2–CKS0)
of the timer control status
register (TCSR)
• Timer counter (TCNT)
—
—
All registers
• Receive data register (RDR)
• Transmit data register (TDR)
• Serial mode register (SMR)
• Serial control register (SCR)
• Serial status register (SSR)
• Bit rate register (BBR)
—
—
Standby control register
(SBYCR)
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