SH7020 Datasheet, PDF (104/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

• Register settings: BARH = H'0003, BARL = H'0147, BBR = H'0054
Conditions set: Address = H'00030147, Bus cycle = CPU, instruction fetch, read (operand size
not included in conditions)
No user break interrupt occurs, because instructions are always fetched from even addresses. If
the first fetched address after a branch is odd and a user break is set on this address, however,
user break exception processing will be carried out after address error exception processing.
CPU Data Access Bus Cycle:
• Register settings: BARH = H'0012, BARL = H'3456, BBR = H'006A
Conditions set: Address = H'00123456, Bus cycle = CPU, data access, write, word
A user break interrupt occurs when word data is written to address H'00123456.
• Register settings: BARH = H'00A8, BARL = H'0391, BBR = H'0066
Conditions set: Address = H'00A80391, Bus cycle = CPU, data access, read, word
No user break interrupt occurs, because word data access is always to an even address.
DMA Cycle:
• Register setting: BARH = H'0076, BARL = H'BCDC, BBR = H'00A7
Conditions set: Address = H'0076BCDC, Bus cycle = DMA, data access, read, long word
A user break interrupt occurs when long word data is read from address H'0076BCDC.
• Register setting: BARH = H'0023, BARL = H'45C8, BBR = H'0094
Conditions set: Address = H'002345C8, Bus cycle = DMA, instruction fetch, read (operand
size not included)
No user break interrupt occurs, because a DMA cycle includes no instruction fetch.
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