SH7020 Datasheet, PDF (297/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

10.5 Interrupts
The ITU has two interrupt sources: input capture/compare match and overflow.
10.5.1 Timing of Setting Status Flags
Timing for Setting IMFA and IMFB in a Compare Match: The IMF bits of the TSR are set to
1 by a compare match signal generated when the TCNT matches a general register. The compare
match signal is generated in the last state in which the values match (when the TCNT is updated
from the matching count to the next count). Therefore, when the TCNT matches the GRA or GRB,
the compare match signal is not generated until the next timer clock input. Figure 10.54 shows the
timing of setting the IMF bits.
CK
TCNT
input clock
TCNT
N
GR
Compare
match signal
IMF
N+1
N
IMI
Figure 10.54 Timing of Setting Compare Match Flags (IMFA, IMFB)
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