SH7020 Datasheet, PDF (13/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

5.3.2 Interrupt Control Register (ICR) .......................................................................... 69
5.4 Interrupt Operation ............................................................................................................ 70
5.4.1 Interrupt Sequence................................................................................................ 70
5.4.2 Stack after Interrupt Exception Processing .......................................................... 72
5.5 Interrupt Response Time.................................................................................................... 73
5.5 Usage Notes ....................................................................................................................... 74
Section 6 User Break Controller (UBC) ...................................................................... 75
6.1 Overview............................................................................................................................ 75
6.1.1 Features ................................................................................................................ 75
6.1.2 Block Diagram...................................................................................................... 75
6.1.3 Register Configuration ......................................................................................... 76
6.2 Register Descriptions......................................................................................................... 77
6.2.1 Break Address Registers (BAR) .......................................................................... 77
6.2.2 Break Address Mask Register (BAMR)............................................................... 78
6.2.3 Break Bus Cycle Register (BBR) ......................................................................... 79
6.3 Operation ........................................................................................................................... 81
6.3.1 Flow of the User Break Operation........................................................................ 81
6.3.2 Break on Instruction Fetch Cycles to On-Chip Memory...................................... 84
6.3.3 Program Counter (PC) Value Saved in User Break Interrupt Exception
Processing............................................................................................................. 84
6.4 Setting User Break Conditions .......................................................................................... 84
6.5 Notes.................................................................................................................................. 86
6.5.1 On-Chip Memory Instruction Fetch ..................................................................... 86
6.5.2 Instruction Fetch at Branches ............................................................................... 86
6.5.3 Instruction Fetch Break ........................................................................................ 87
Section 7 Clock Pulse Generator (CPG) ..................................................................... 89
7.1 Overview............................................................................................................................ 89
7.2 Clock Source...................................................................................................................... 89
7.2.1 Connecting a Crystal Resonator ........................................................................... 89
7.2.2 External Clock Input ............................................................................................ 90
7.3 Usage Notes ....................................................................................................................... 91
Section 8 Bus State Controller (BSC) ........................................................................... 93
8.1 Overview............................................................................................................................ 93
8.1.1 Features ................................................................................................................ 93
8.1.2 Block Diagram...................................................................................................... 93
8.1.3 Pin Configuration ................................................................................................. 95
8.1.4 Register Configuration ......................................................................................... 95
8.1.5 Overview of Areas................................................................................................ 96
8.2 Register Descriptions......................................................................................................... 97
8.2.1 Bus Control Register (BCR) ................................................................................ 97