SH7020 Datasheet, PDF (338/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

TPC Output Non-Overlap Operation (Four-Phase Complementary Non-Overlap Output)
(figure 11.7):
1. Set GRA and GRB of the ITU that serves as output trigger in the output compare registers. Set
the cycle in the GRB and the non-overlap cycle time in the GRA and select to clear the counter
upon compare match B. Set the IMIEA bit of TIER to 1 to enable the IMIA interrupt.
2. Write H'FFFF in the PBCR1, write H'FF in the NDERB, and set G3CMS1, G3CMS0,
G2CMS1 and G2CMS0 in the TPCR to set the ITU compare match selected in step 1 as the
output trigger. Set the G3NOV and G2NOV bits in the TPMR to 1 to set the non-overlap
operation. Write output data H'95 in the NDRB.
3. When the selected ITU channel starts operating and a GRB compare-match occurs, 1 output
changes to 0 output; when a GRA compare match occurs, 0 output changes to 1 output. (The
change from 0 output to 1 output is delayed by the value set in GRA.) The IMIA interrupt
service routine writes the next output data (H'65) in the NDRB.
4. Four-phase complementary non-overlap output can be obtained by writing H'59, H'56, H'95…
at successive IMIA interrupts. If the DMA controller is set for activation by compare-match,
pulse output can be obtained without loading the CPU.
322 RENESAS