SH7020 Datasheet, PDF (55/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

Table 2.13 Arithmetic Instructions (cont)
Instruction
Instruction Code
Operation
Execution
Cycles
T bit
EXTS.W Rm,Rn
0110nnnnmmmm1111 A word in Rm is sign- 1
—
extended → Rn
EXTU.B Rm,Rn
0110nnnnmmmm1100 A byte in Rm is zero- 1
—
extended → Rn
EXTU.W Rm,Rn
0110nnnnmmmm1101 A word in Rm is zero- 1
—
extended → Rn
MAC.W @Rm+,@Rn+ 0100nnnnmmmm1111 Signed operation of 3/(2)*
—
(Rn) × (Rm) + MAC
→ MAC
MULS Rm,Rn
0010nnnnmmmm1111 Signed operation of 1–3*
—
Rn × Rm → MAC
MULU Rm,Rn
0010nnnnmmmm1110 Unsigned operation 1–3*
—
of Rn × Rm → MAC
NEG Rm,Rn
0110nnnnmmmm1011 0–Rm → Rn
1
—
NEGC Rm,Rn
0110nnnnmmmm1010 0–Rm–T → Rn,
1
Borrow → T
Borrow
SUB Rm,Rn
0011nnnnmmmm1000 Rn–Rm → Rn
1
—
SUBC Rm,Rn
0011nnnnmmmm1010 Rn–Rm–T → Rn,
1
Borrow → T
Borrow
SUBV Rm,Rn
0011nnnnmmmm1011 Rn–Rm → Rn,
1
Underflow → T
Underflow
Note: The normal minimum number of execution cycles (The number in parenthesis in the
number of cycles when there is contension with preceding/following instructions).
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