SH7020 Datasheet, PDF (103/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

6.3.2 Break on Instruction Fetch Cycles to On-Chip Memory
On-chip memory (on-chip ROM and RAM) is always accessed 32 bits each bus cycle. Two
instructionsare therefore fetched in a bus cycle from on-chip memory . Although only a single bus
cycle occurs for the two-instruction fetch, a break can be set on either instruction by placing the
corresponding address in the break address registers (BAR). In other words, to break the second of
the two instructions fetched, set its start address in the BAR. The break will then occur after the
first instruction executes.
6.3.3 Program Counter (PC) Value Saved in User Break Interrupt Exception Processing
Break on Instruction Fetch: The program counter (PC) value saved in user break interrupt
exception processing for an instruction fetch is the address set as the break condition. The user
break interrupt is generated before the fetched instruction is executed. If a break condition is set on
the fetch cycle of a delayed slot instruction immediately following a delayed branch instruction or
on the fetch cycle of an instruction that follows an interrupt-disabling instruction, however, the
user break interrupt is not accepted immediately, so the instruction is executed. The user break
interrupt is not accepted until immediately after that instruction. The PC value that will be saved is
the start address of the next instruction that is able to accept the interrupt.
Break on Data Access (CPU/DMAC): The program counter (PC) value is the top address of the
next instruction after the last executed instruction at the time when the user break exception
processing is activated. When data access (CPU/DMAC) is set as a break condition, the place
where the break will occur cannot be specified exactly. The break will occur at the instruction
fetched close to where the data access that is to receive the break occurs.
6.4 Setting User Break Conditions
CPU Instruction Fetch Bus Cycle:
• Register settings: BARH = H'0000, BARL = H'0404, BBR = H'0054
Conditions set: Address = H'00000404, Bus cycle = CPU, instruction fetch, read (operand size
not included in conditions)
A user break interrupt will occur immediately before the instruction at address H'00000404. If
the instruction at address H'00000402 can accept an interrupt, the user break exception
processing will be executed after that instruction is executed. The instruction at H'00000404
will not be executed. The value saved to PC is H'00000404.
• Register settings: BARH = H'0015, BARL = H'389C, BBR = H'0058
Conditions set: Address = H'0015389C, Bus cycle = CPU, instruction fetch, write (operand
size not included in conditions)
No user break interrupt occurs, because no instruction fetch cycle is ever a write cycle.
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