SH7020 Datasheet, PDF (149/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

CK
A21–A0
CSn
Read
RD
AD15–AD0
T1
Tw (wait state)
T2
WRH, WRL
Write
AD15–AD0
WAIT
Figure 8.13 Wait State Timing for External Memory Space Access (2 states plus wait states
from WAIT signal)
Areas 0, 2 and 6 have long wait functions. When the corresponding bits in WCR1 and WCR2 are
cleared to 0, the access cycle is 1 state plus the number of long wait states (set in WCR3,
selectable between 1 and 4) and the WAIT pin input signal is not sampled. When the bits are set to
1, the WAIT signal is sampled and the number of states is 1 plus the number of long wait states
plus the number of wait states in the WAIT signal. The WAIT signal is sampled at the rise of the
system clock (CK) directly preceding the last long wait state and the wait states are inserted as
long as the level is low. When a high level is detected, it shifts to the final long wait state. Figure
8.14 shows the wait state timing when accessing the external memory spaces of areas 0, 2, and 6.
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