SH7020 Datasheet, PDF (133/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

8.3 Address Space Subdivision
8.3.1 Address Spaces and Areas
Figure 8.3 shows the address format used in this LSI.
4 Gbyte space
128 Mbyte space
16 Mbyte space
4 Mbyte space
A31–A28 A27 A26–A24 A23,A22 A21
A0
Output address:
Output from address pins
A21–A0
Ignore: Only valid when the address multiplex
function is being used in the DRAM space (area 1);
not output in other cases. When not output,
becomes shadow.
Area selection:
Decoded to become chip select signals CS0–CS7 for areas 0–7
Basic bus width selection:
Not output externally, but used for basic bus width selection
When 0, (H'0000000–H'7FFFFFF), the basic bus width is 8 bits.
When 1, (H'8000000–H'FFFFFFF) the basic bus width is 16 bits.
Ignore: Always ignore, not output externally
Figure 8.3 Address Format
Since this LSI uses a 32-bit address, 4 Gbytes of space can be accessed on the architecture;
however, the upper 4 bits (A31–A28) are always ignored and not output. Bit A27 is basically only
used for switching the bus width. When the A27 bit is 0 (H'0000000–H'7FFFFFF), the bus width
is 8 bits; when the A27 bit is 1 (H'8000000–H'FFFFFFF), the bus width is 16 bits. Of the
remaining 27 bits (A26–A0), a total 128 Mbyte can thus be accessed.
The 128 Mbyte space is subdivided into 8 areas (areas 0–7) of 16 Mbytes each according to the
values of bits A26–A24. The space with bits A26–A24 as 000 is area 0 and the space 111 is area 7.
The A26–A24 bits are decoded and become the chip select signals (CS0–CS7) of the
corresponding areas 0–7 and output. Table 8.6 shows how the space is divided.
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