SH7020 Datasheet, PDF (360/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

13.2.4 Transmit Data Register
The transmit data register (TDR) is an eight-bit register that stores data for serial transmission.
When the SCI detects that the transmit shift register (TSR) is empty, it moves transmit data written
in the TDR into the TSR and starts serial transmission. Continuous serial transmission is possible
by writing the next transmit data in the TDR during serial transmission from the TSR.
The CPU can always read and write the TDR. The TDR is initialized to H'FF by a reset or in
standby mode.
Bit: 7
6
5
4
3
2
1
0
Bit name:
Initial value: 1
1
1
1
1
1
1
1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
13.2.5 Serial Mode Register
The serial mode register (SMR) is an eight-bit register that specifies the SCI serial communication
format and selects the clock source for the baud rate generator.
The CPU can always read and write the SMR. The SMR is initialized to H'00 by a reset or in
standby mode.
Bit: 7
Bit name: C/A
Initial value: 0
R/W: R/W
6
5
CHR
PE
0
0
R/W R/W
4
3
2
1
0
O/E STOP MP CKS1 CKS0
0
0
0
0
0
R/W R/W R/W R/W R/W
• Bit 7 (communication mode (C/A)): C/A selects whether the SCI operates in the asynchronous
or clocked synchronous mode.
Bit 7: C/A
0
1
Description
Synchronous mode (initial value)
Clocked synchronous mode
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