SH7020 Datasheet, PDF (163/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

CK
A21–
A0
RAS
CAS
WR
AD15–
AD0
Access A (read)
Access B (write)
Silent
T_p
T_r
T_c
T_c
cycle
T_c
T_c
Column Column
address A-1 address A-2
Column Column
address B-1 address B-2
Row address
Read data A-1 Read data A-2 Write data B-1 Write data B-2
Note: Access A and B are examples of 32-bit data accesses in their respective 16-bit bus width
spaces.
Figure 8.25 Short Pitch High-Speed Page Mode (When read and write cycle continues with
the same row address)
The high-level duty of the CAS signal can be selected in the short pitch high-speed page mode
using the CAS duty bit (CDTY) in the DCR. When the CDTY bit is cleared to 0, high-level
duty is 50% of the TC state; when CDTY is set to 1, it is 35% of the T_C state.
• Long-pitch, high-speed page mode: When the RW1, WW1, DRW1, and DWW1 bits in WCR1
and WCR2 are set to 1, and the corresponding DRAM access cycle is continuing, the CAS
signal and column address output cycles (2 states) continue as long as the row addresses
continue to match. When the WAIT signal is detected at the low level, the second cycle of the
column address output cycle is repeated as the wait state. Figure 8.26 shows the timing for the
long pitch high-speed page mode. See section 20.3.3, Bus Timing, for more information about
the timing.
RENESAS 145