SH7020 Datasheet, PDF (191/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

9.2 Register Descriptions
9.2.1 DMA Source Address Registers 0–3 (SAR0–SAR3)
DMA source address registers 0–3 (SAR0–SAR3) are 32-bit read/write registers that specify the
source address of a DMA transfer. During a DMA transfer, these registers indicate the next source
address (in single-address mode, SAR is ignored in transfers from external devices with DACK to
memory-mapped external devices or external memory).
The initial value after resets or in standby mode is undefined.
Bit: 31
30
29
28
27
26
25
24
Bit name:
Initial value: —
—
—
—
—
—
—
—
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 23
22
21
20
…
0
Bit name:
…
Initial value: —
—
—
—
…
—
R/W: R/W R/W R/W R/W
…
R/W
9.2.2 DMA Destination Address Registers 0–3 (DAR0–DAR3)
DMA destination address registers 0–3 (DAR0–DAR3) are 32-bit read/write registers that specify
the destination address of a DMA transfer. During a DMA transfer, these registers indicate the
next destination address (in single-address mode, DAR is ignored in transfers from memory-
mapped external devices or external memory to external devices with DACK). The initial value
after resets or in standby mode is undefined.
Bit: 31
30
29
28
27
26
25
24
Bit name:
Initial value: —
—
—
—
—
—
—
—
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 23
22
21
20
…
0
Bit name:
…
Initial value: —
—
—
—
…
—
R/W: R/W R/W R/W R/W
…
R/W
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