SH7020 Datasheet, PDF (226/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

6. Notes on use of the SLEEP command
a. Operation contents
When the bus cycle of DMAC is entered immediately after executing the SLEEP
command, there are cases when the DMA transfer is carried out correctly.
b. Countermeasure
• Stop the operation (for exemple, clearing of the DMA enable bit (DE) of the DMA
channel control register(CHCRn)) before entering SLEEP.
• When using DMAC during SLEEP, operate DMAC after releasing SLEEP through
interruption.
In cases when the CPU does not carry out any other processing but is waiting for DMAC to end its
transfer during DMAC operation, do not use the SLEEP command, but use the transfer end flag bit
(TE) of the channel DMA control register and the polling software loop.
Phenomenon: If the bus cycle of DMAC is entered immediately after executing the SLEEP
command, the bus cycle of DMAC may conflict with that of CPU.
Address bus _CPU
CPU
CPU DMAC DMAC CPU
CPU
Fetch cycle of
SLEEP command
This is in itself a DMAC cycle but
involves CPU operation.
Accordingly, the bus cycle of DMAC which has conflicted with that of CPU may malfunction.
7. Sampling of DREQ
If DREQ is set to level detection in the DMA cycle steal mode, sampling of DREQ may take
place before DACK is output. Note that some system configurations involve unnecessary
DMA transfers.
• Operation
As shown in Figure 9.16, sampling of DREQ is carried out immediately before the leading
edge of the third-state clock (CK) after completion of the bus cycle preceding the DMA bus
cycle where DACK is output.
If DACK is output after the third state of the DMA bus cycle, sampling of DREQ must be
carried out before DACK is output.
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