SH7020 Datasheet, PDF (354/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

12.4 Usage Notes
12.4.1 TCNT Write and Count Up Contention
If a timer counter clock pulse is generated during the T3 state of a write cycle to the TCNT, the
write takes priority and the timer counter is not incremented (figure 12.8).
TCNT write cycle
T1
T2
T3
CK
Address
TCNT address
Internal
write signal
TCNT
input clock
TCNT
N
M
Counter write data
Figure 12.8 Contention between TCNT Write and Increment
12.4.2 Changing CKS2-CKS0 Bit Values
If the values of bits CKS2–CKS0 are altered while the WDT is running, the count may increment
incorrectly. Always stop the watchdog timer (by clearing the TME bit to 0) before changing the
values of bits CKS2–CKS0.
12.4.3 Changing Watchdog Timer/Interval Timer Modes
To prevent incorrect operation, always stop the watchdog timer (by clearing the TME bit to 0)
before switching between interval timer mode and watchdog timer mode.
RENESAS 338