SH7020 Datasheet, PDF (486/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

Table 19.8 Bus Timing (3) (cont)
Conditions: V_CC = 3.0 to 5.5 V, V_SS = 0 V, φ = 12.5 MHz, Ta = –20 to +75°C*
*: Normal products. Ta = –40 to +85°C for wide-temperature range products
Item
Symbol Min Max
Unit Figures
DACK0, DACK1 delay time 1 t_DACD1 — 40
DACK0, DACK1 delay time 2 t_DACD2 — 40
DACK0, DACK1 delay time 3 t_DACD3 — 40
ns 19.21, 19.22, 19.24–
ns ^{19.27, 19.32, 19.33}
ns 19.22, 19.26, 19.27,
19.32
DACK0, DACK1 delay time 4 t_DACD4
DACK0, DACK1 delay time 5 t_DACD5
Read delay time 35% duty^*1 t_RDD
50% duty
Data setup time for CAS
t_DS
CAS setup time for RAS
t_CSR
Row address hold time
t_RAH
Write command hold time t_WCH
Write command 35% duty^*1 t_WCS
setup time
50% duty t_WCS
Access time from CAS
precharge^*4
t_ACP
— 40
— 40
— t_cyc × 0.35 + 35
— t_cyc × 0.5 + 35
0*³ —
10 —
10 —
15 —
0—
0—
tcyc —
-20
ns 19.24, 19.25
ns
ns 19.21, 19.22, 19.24-
ns ^{19.28, 19.32}
ns 19.24, 19.26
ns 19.29–19.31
ns 19.24, 19.26
ns
ns 19.24
ns
ns 19.25
Notes: 1. When frequency is 10 MHz or more.
2. n is the number of wait cycles.
3. –5 ns for parity output of DRAM long-pitch access
4. It is not necessary to meet the t_RDS specification as long as the access time
specification is met.
RENESAS 476