SH7020 Datasheet, PDF (141/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

Areas 2–4 are always used as external memory space. The bus width is 8 bits when the A27 bit is
0 and 16 bits when it is 1. A23 and A22 bits are not output and the shadow is in 4-Mbyte units.
When areas 2–4 are accessed, the CS2, CS3, and CS4 signals are valid. Area 2 has a long wait
function, so between 1 and 4 states can be selected for the number of long waits inserted into the
bus cycle using the bits A02LW1 and A02LW0 of WCR3.
H'A000000
Logical address space
H'2000000
H'A3FFFFF
H'A400000
H'23FFFFF
H'2400000
Shadow
H'A7FFFFF
H'A800000
H'27FFFFF
H'2800000
Shadow
Actual space
External
memory space
(4 Mbytes)
H'ABFFFFF
H'AC00000
H'2BFFFFF
H'2C00000
Shadow
• Valid addresses A21–A0
(A23 and A22 not output)
• CS2 valid
• Long wait function
H'AFFFFFF
Shadow
H'2FFFFFF
16-bit space
8-bit space
Figure 8.7 Memory Map of Area 2
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