SH7020 Datasheet, PDF (300/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

10.5.3 Interrupt Sources and Activating the DMAC
The ITU has compare match/input capture A interrupts, compare match/input capture B interrupts
and overflow interrupts for each channel. Each of the fifteen of these three types of interrupts are
allocated their own independently vectored addresses. When the interrupt’s interrupt request flag
is set to 1 and the interrupt enable bit is set to 1, the interrupt is requested.
The channel priority order can be changed with the interrupt controller. For more information, see
section 5, Interrupt Controller. The compare match/input capture A interrupts of channels 0–3 can
start the DMAC to transfer data. Table 10.17 lists the interrupt sources.
Table 10.17 ITU Interrupt Sources
Interrupt
Channel Source Description
DMAC
Priority
Activation Order*
0
IMIA0 Compare match or input capture A0
Yes
High
IMIB0 Compare match or input capture B0
No
↑
OVI0
Overflow 0
No
1
IMIA1 Compare match or input capture A1
Yes
IMIB1 Compare match or input capture B1
No
OVI1
Overflow 1
No
2
IMIA2 Compare match or input capture A2
Yes
IMIB2 Compare match or input capture B2
No
OVI2
Overflow 2
No
3
IMIA3 Compare match or input capture A3
Yes
IMIB3 Compare match or input capture B3
No
OVI3
Overflow 3
No
4
IMIA4 Compare match or input capture A4
No
IMIB4 Compare match or input capture B4
No
↓
OVI4
Overflow 4
No
Low
Note: Indicates the initial status following reset. The ranking of channels can be altered using the
interrupt controller.
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