SH7020 Datasheet, PDF (306/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

10.6.6 Contention between General Register Read and Input Capture
If an input capture signal is generated during the T3 state of a general register read cycle, the value
before input capture is read. The timing is shown in figure 10.63.
GR read cycle
T1
T2
T3
CK
Address
Internal read
signal
Input capture
signal
GR
GR address
X
M
Internal
data bus
X
Figure 10.63 Contention between General Register Read and Input Capture
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