SH7020 Datasheet, PDF (80/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

Section 5 Interrupt Controller (INTC)
5.1 Overview
The interrupt controller (INTC) determines the priority of interrupt sources and controls interrupt
requests to the CPU. INTC has registers for assigning priority levels to interrupt sources. These
registers handle interrupt requests according to user-established priorities.
5.1.1 Features
The interrupt controller has the following features:
• 16 settable priority levels: Five interrupt priority registers can set 16 levels of interrupt
priorities for IRQ and on-chip peripheral interrupt sources.
• The INTC has an NMI input level T bit that indicates NMI pin status. By reading this bit with
the interrupt exception service routine, the pin status can be checked for use in a noise
canceller function.
• The interrupt controller can notify external devices (via the IRQOUT pin) that an onchip
interrupt has been occured. In this way an external device can, for example, be informed if an
on-chip interrupt occurs while the chip is operating in a bus-released mode and the bus has
been requested.
5.1.2 Block Diagram
Figure 5.1 is a block diagram of the interrupt controller.
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