SH7020 Datasheet, PDF (97/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

BARL: Break address register L.
Bit: 15
14
13
12
11
10
9
8
Bit name: BA15 BA14 BA13 BA12 BA11 BA10 BA9 BA8
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7
6
5
4
3
2
1
0
Bit name: BA7 BA6 BA5 BA4 BA3 BA2 BA1 BA0
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
• BARL Bits 15–0 (break address 15–0 (BA15–BA0)): BA15–BA0 store the lower bit values
(bits 15–0) of the address of the break condition.
6.2.2 Break Address Mask Register (BAMR)
The two break address mask registers—break address mask register H (BAMRH) and break
address mask register L (BARML)—together form a single group. Both are 16-bit read/write
registers. BAMRH determines which of the bits in the break address set in BARH are masked.
BAMRL determines which of the bits in the break address set in BARL are masked. A reset
initializes BAMRH and BARML to H'0000. They are not initialized in the standby mode.
BAMRH: Break address mask register H.
Bit: 15
14
13
12
11
10
9
8
Bit name: BAM31 BAM30 BAM29 BAM28 BAM27 BAM26 BAM25 BAM24
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7
6
5
4
3
2
1
0
Bit name: BAM23 BAM22 BAM21 BAM20 BAM19 BAM18 BAM17 BAM16
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
• BAMRH bits 15–0 (break address mask 31–16 (BAM31–BAM16)): BAM31–BAM16 specify
whether bits BA31–BA16 of the break address set in BARH are masked or not.
78 RENESAS