SH7020 Datasheet, PDF (211/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

• Dual Address Mode
In the dual address mode, both the transfer source and destination are accessed (selectable) by
an address. The source and destination can be located externally or internally. The source is
accessed in the read cycle and the destination in the write cycle, so the transfer is performed in
two separate bus cycles. The transfer data is temporarily stored in the DMAC. Figure 9.8
shows an example of a transfer between two external memories in which data is read from one
memory in the read cycle and written to the other memory in the following write cycle.
External data bus
SuperH microcomputer
2
DMAC
External
memory
External
memory
1
: Data flow
1: Read cycle
2: Write cycle
Figure 9.8 Data Flow in Dual Address Mode
In the dual address mode transfers, external memory, memory-mapped external devices, on-
chip memory and on-chip peripheral modules can be mixed without restriction. Specifically,
this enables the following transfer types:
1. External memory and external memory transfer
2. External memory and memory-mapped external devices transfer
3. Memory-mapped external devices and memory-mapped external devices transfer
4. External memory and on-chip memory transfer
5. External memory and on-chip peripheral modules (excluding the DMAC) transfer
6. Memory-mapped external devices and on-chip memory transfer
7. Memory-mapped external devices and on-chip peripheral modules (excluding the DMAC)
transfer
8. On-chip memory and on-chip memory transfer
9. On-chip memory and on-chip peripheral modules (excluding the DMAC) transfer
10. On-chip peripheral modules (excluding the DMAC) and on-chip peripheral modules
(excluding the DMAC) transfer
194 RENESAS