SH7020 Datasheet, PDF (90/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

operation described in "Clearing Conditions" is performed.
Program
execution state
No
Interrupt?
Yes
NMI?
No
Yes
User break?
No
Yes
Level 15
No
interrupt?
Yes
IRQOUT low ^*1
Pushes SR onto stack
Pushes PC onto stack
Yes
I3 to I0 ≤
level 14?
No Yes
Level 14
interrupt?
Yes
I3 to I0 ≤
level 13?
No
Level 1 ^No
interrupt?
Yes
No Yes
I3 to I0 =
level 0?
No
Copies level of accep-
tance from I3 to I0
IRQOUT high ^*2
Reads exception
vector table
Branches to exception
service routine
I3 to I0 : Interrupt mask bits of status register
Notes : *1. IRQOUT is the same signal as the interrupt request signal to the CPU (Figure 5.1).
The pin IRQOUT return to the high level when the interrupt controller has accepted
the interrupt of a level higher than the I3 to I0 bits of the status register in the CPU.
*2. If the accepted interrupt is edge-sensed, the pin IRQOUT returns to the high level
when the instruction to be executed by the CPU is replaced by the interrupt
exception processing (before the status register is saved to the stack ).
If the interrupt controller has accepted another interrupt of a level higher than the
current interrupt. and has requested the interrupt to the CPU, however, the pin
IRQOUT remains low.
Figure 5.2 Flowchart of Interrupt Operation
RENESAS 71