SH7020 Datasheet, PDF (328/509 Pages) Renesas Technology Corp – SuperH™ RISC engine

Bit: 7
6
5
4
3
2
1
0
Bit name: NDER7 NDER6 NDER5 NDER4 NDER3 NDER2 NDER1 NDER0
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
• Bits 7–0 (next data enable 7–0 (NDER7–NDER0)): NDER7–NDER0 select enable/disable for
TPC output groups 1 and 0 (TP7–TP0) in bit units.
Bit 7–0: NDER7–NDER0 Description
0
Disables TPC outputs TP7–TP0 (transfer from NDR7–NDR0 to PB7–
PB0 is disabled) (initial value)
1
Enables TPC outputs TP7–TP0 (transfer from NDR7–NDR0 to PB7–
PB0 is enabled)
11.2.6 Next Data Enable Register B (NDERB)
NDERB is an eight-bit read/write register that enables TPC output groups 3 and 2 (TP15–TP8) on
a bit-by-bit basis.
When the bits enabled for TPC output by NDERB generate the ITU compare match selected in the
TPC output control register, the value of the next data register B (NDRB) is automatically
transferred to the corresponding PBDR bits and the output value is updated. For disabled bits,
there is no transfer and the output value does not change. When reset, NDERB is initialized to
H'00. It is not initialized by standby mode.
Bit: 7
6
5
4
3
2
1
0
Bit name: NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER8
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
• Bits 7–0 (next data enable 15–8 (NDER15–NDER8)): NDER15–NDER8 select enable/disable
for TPC output groups 3 and 2 (TP15–TP8) in bit units.
Bit 7–0:
NDER15–NDER8
0
1
Description
Disables TPC outputs TP15–TP8 (transfer from NDR15–NDR8 to
PB15–PB8 is disabled) (initial value)
Enables TPC outputs TP15–TP8 (transfer from NDR15–NDR8 to
PB15–PB8 is enabled)
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